ELECTRONICS DESIGN COURSE
Fundamentals of CPLD/FPGA System Design with Verilog/VHDL Language
This course is targeted for those who begin to learn complex programmable logic device (CPLD). The course is based on VHDL language. Students will learn how to use VHDL library, how to build entities and architectures and how to debug after completing a program. This course combines both theoretical lecture and hand-on practices on study board (based on Altera EPM240T100C5 chip).
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Pre-requisition: Digital electronics
Duration: 30 hours / Part time
Commencing/End date: Schedule
Mode of Delivery: Instructor led, classroom based training
Method of assessment: Exercise and project
Location: St.Hua Classroom
Fee: SGD1400.00 Inclusive Registration Fee and Material Fee
Average Teacher to Student Ratio: 1:10
Industrial Attachment: NA
Instructor: Mr. Tang Fan / Mr. Adam Ye |
Content: |
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- Concept of CPLD and FPGA, basic structure of VHDL.
- Familiar with Moore State Machine and usage of RTL viewer.
- VHDL design process of a counter and how to write program to the study board.
- A design example on dual in-line package (DIP) switch and dynamic LED display.
- Detecting of keying and display control.
- Eliminating jitter of keys
- A design example of traffic light and how to control timing.
- A design example of dynamic display and how to control dot matrix display.
- How to use ADC0804 to collect voltage information and convert to digital data.
- Sine wave generation, theory of Direct Digital Synthesizer (DDS)
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